1. Field of the Invention
The present invention relates generally to a power semiconductor device such as a diode, a MOSFET (field-effect insulated gate transistor) and an IGBT (a conductivity modulation-type transistor) for use in a power converter or the like and, more particularly, to a semiconductor device and a method for manufacturing the same that are suitable for the use of a FZ (floating zone) wafer.
2. Description of Related Art
An epitaxial diode in FIG. 6 is manufactured by using an epitaxial wafer that is formed by growing a low-concentration n-type epitaxial layer, which functions as an nxe2x88x92 drift layer 3, on a high-concentration n-type silicon substrate forming an n+ cathode layer 1. The nxe2x88x92 drift layer 3 carries drift current in an ON state. In a blocking mode (an OFF state), a depletion layer spreads into the n+ cathode layer 1 from a pn junction between the nxe2x88x92 drift layer 3 and a p+ anode layer 4 to thereby assure a withstand voltage. The n+ cathode layer 1 has a function of preventing the depletion layer from reaching a cathode electrode 9 in the blocking mode and achieving a favorable ohmic contact with the cathode electrode 9. The epitaxial diode using the epitaxial wafer has the high-concentration n-type silicon substrate and the nxe2x88x92 drift layer 3, which is grown on the high-concentration n-type silicon substrate by an epitaxial method. Therefore, an impurity concentration inclines sharply in the n+ cathode layer 1 and at the boundary between the n+ cathode layer 1 and the nxe2x88x92 drift layer 3, as shown in the graph representing the longitudinal dependency of a doping concentration in FIG. 6. Thus, there is a favorable tradeoff relationship between a forward voltage and the withstand voltage. The epitaxial wafer, however, is expensive and, therefore, it is costly to manufacture the epitaxial diode.
On the other hand, a DW diode in FIG. 7 is manufactured from a DW wafer that is fabricated by diffusing a high-concentration phosphorus from the reverse side of a low-concentration n-type silicon substrate (FZ wafer), which functions as the nxe2x88x92 drift layer 3, to form an n+ cathode layer 1a. The DW wafer is less expensive than the epitaxial wafer because the DW wafer does not require a growing step by an epitaxial method. Thus, the use of the DW wafer can reduce the cost of manufacturing the DW diode. As shown in the graph representing the longitudinal dependency of doping concentration in FIG. 7, however, the impurity concentration inclines gently in the n+ cathode layer 1a and at the boundary between the n+ cathode layer and the nxe2x88x92 drift layer 3. Therefore, there is an unfavorable tradeoff relationship between the forward voltage and the withstand voltage.
A non-punch through IGBT in FIG. 8 is manufactured by using an inexpensive FZ wafer forming an nxe2x88x92 drift layer 33. An element active region (e.g., a p+ base region 34, an n+ emitter region 35, a gate oxide film 36 or a gate electrode 37) and an emitter electrode 38 are formed at the right side of the FZ wafer. The reverse side of the wafer is treated to reduce it to a predetermined thickness and, then, the reverse side of the wafer is implanted with boron ions, a portion of the implanted ions being activated by annealing at a low temperature of not greater than 400xc2x0 C. This forms a p+ collector layer 31. To acquire a sufficient withstand voltage in a forward blocking mode, the nxe2x88x92 drift layer 33 must have enough thickness to prevent the depletion layer spreading from the pn junction between the p+ base region 34 and the nxe2x88x92 drift layer 33 from reaching the p+ collector layer 31. If the nxe2x88x92 drift layer 33 is thick, however, the resistance is increased to significantly lower the voltage in the ON state of the IGBT. This makes it difficult to achieve a large volume of power and increases the number of carriers accumulated in the nxe2x88x92 drift layer 33. In addition, there is a great turnoff loss. Although the non-punch through IGBT can be manufactured at a low cost, it cannot achieve high performance.
On the other hand, a punch through IGBT in accordance with FIG. 9 is manufactured by using an epitaxial wafer, which is fabricated by growing a high-concentration n-type epitaxial layer functioning as an n+ buffer 32 on a high-concentration p type substrate forming a p+ collector layer 31a, and growing a low-concentration n-type epitaxial layer functioning as an nxe2x88x92 drift layer 33a on the high-concentration n-type epitaxial layer. In a forward blocking mode, a depletion layer spreads slowly in the high impurity concentration n+ buffer layer 32, and it is therefore possible to acquire a high withstand voltage even in the thin nxe2x88x92 drift layer 33a. Therefore, the voltage of the punch through IGBT is lowered by a smaller degree in the ON state, as compared with the non-punch through IGBT with the same withstand voltage. In addition, the punch through IGBT increases the current capacity and reduces the turnoff loss. However, it costs more to manufacture the punch through IGBT, since there is the need to use an epitaxial wafer.
A power semiconductor device, such as a diode or a MOSFET, has recently achieved high characteristics, but it is still desired to further reduce costs. To reduce the costs, it is advantageous to adopt an inexpensive FZ wafer in a wafer process. In order to achieve high characteristics, the reverse side of the FZ wafer, which has a surface active region, such as the p+ anode layer 4 and the anode electrode 8 thereof, is treated to reduce it to a predetermined thickness; phosphorus and arsenic ions are implanted from the reverse side; and an annealing process is performed to thereby activate the impurities and form an n+ cathode layer. Since the maximum concentration point can be set at a deep portion by the ion implantation method, the impurity concentration inclines sharply in the n+ cathode layer and at the boundary between the n+ cathode layer and the nxe2x88x92 drift layer. Therefore, the power semiconductor device can be expected to achieve high characteristics of the same level as achieved by an epitaxial diode.
The annealing temperature should be not less than about 1000xc2x0 C. to activate the phosphorus or arsenic atoms sufficiently in the silicon wafer. Thus, the annealing must be completed before the aluminum anode electrode 8, which has a low fusing point (about 700xc2x0 C.), is adhered to the surface of the wafer. Even if the annealing is performed before the adhesion of the anode electrode 8, the wafer bows greatly when the thin wafer (after it has been treated to reduce its thickness) is annealed at high temperatures of 1000xc2x0 C. or more. It is therefore impossible to perform a photolithography process to form the anode electrode 8 at a subsequent stage. For this reason, the inexpensive FZ wafer cannot be used in the wafer process. This problem applies not only to the above-mentioned longitudinal diode cathode layer, but also to the formation of a general ohmic contact layer (high impurity concentration layer) at the outermost surface of the reverse side, such as a drain layer of a longitudinal MOSFET or a collector layer of an IGBT (conductivity modulation-type MOSFET) of a non-punch through IGBT.
Accordingly, it is an object of the present invention to provide a semiconductor device, which can be manufactured with less trouble by using the inexpensive FZ wafer in the wafer process and has a sharp impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration layer and a low impurity concentration drift layer, thereby achieving both low cost and high performance.
In recent years, power semiconductor devices such as IGBT devices achieve high characteristics, but it is also desired to reduce costs further. To reduce cost, it is advantageous to adopt an inexpensive FZ wafer in a wafer process. To achieve high characteristics, an n+ buffer layer 32 must be formed. For example, the reverse side of the FZ wafer, which has a surface active region, such as a p+ anode layer 4 and the anode electrode 8 thereof, is treated to reduce it to a predetermined thickness; Ions, such as phosphorus or arsenic ions, are implanted from the reverse side; and an annealing process is performed to activate the implanted impurities to form an n+ cathode layer.
The annealing temperature, however, must be 1000xc2x0 C. or more to activate the phosphorus or arsenic atoms sufficiently in the silicon wafer. Thus, the annealing must be completed before the aluminum emitter electrode 38 with a low fusing point (about 700xc2x0 C.) becomes adhered to the surface of the wafer. Even if the annealing is performed prior to the adhesion of the emitter electrode 38, the wafer bows greatly when the thin wafer (after it has been treated to reduce its thickness) is annealed at a high temperature of 1000xc2x0 C. or more. It is therefore impossible to perform a photolithography process to form the emitter electrode 38 at a subsequent stage. For this reason, it has been impossible to use the inexpensive FZ wafer in the conventional wafer process. Accordingly, the p+ collector layer 31 must be formed by annealing at a low temperature in the case of the non-punch through IGBT in FIG. 8.
Accordingly, it is an object of the present invention to provide a semiconductor device that can be manufactured with less trouble by using an inexpensive FZ wafer in the wafer process and that can form a high impurity concentration buffer layer and reverse conducting high impurity concentration layer at the outermost portion of the reverse side without any significant trouble, even after the formation of the element active region and the electrode thereof on the right side of the wafer, thereby achieving both low cost and high performance.
The above object can be accomplished by forming a high impurity concentration layer at the outermost portion of the reverse side (the second principal side) by a low-temperature process.
According to the first arrangement, a semiconductor device, which uses a first-conductivity-type low impurity concentration substrate forming a first-conductivity-type low impurity concentration drift layer, and which comprises an element active region and a first electrode thereof formed at a first principal side of the substrate, and a high impurity concentration layer and a second electrode thereof formed at an outermost portion of a second principal side of the substrate, is characterized in that: the high impurity concentration layer is composed of an n-type defect layer.
A method for manufacturing the semiconductor device, which uses the n-type defect layer at the outermost portion of the second principal side as the high concentration n-type semiconductor layer, such as a contact layer, comprises the steps of: forming the element active region and the first electrode on the first principal side of the substrate; treating the second principal side of the substrate to reduce it to a predetermined thickness; irradiating protons from the second principal side; and performing an annealing process to thereby form the n-type defect layer. An annealing temperature (not greater than about 700xc2x0 C.) for activating the n-type defect layer may be lower than a fusing point of a first electrode layer made of aluminum or the like. It is therefore possible to form the n-type defect layer at the second principal side, even after the adhesion of the first electrode at the first principal side, without any significant trouble. This semiconductor device can be manufactured at low cost, since it is possible to use an inexpensive n-type low impurity concentration FZ wafer. Due to the use of a proton ion implantation method, the range can be long and the maximum concentration point can be set in a deep portion. Thus, the impurity concentration inclines sharply in the n-type defect layer as the high impurity concentration layer and at the boundary between the n defect layer and the low impurity concentration drift layer. This achieves a high characteristic of the same level as a semiconductor device that is manufactured by using an epitaxial wafer.
The annealing process is preferably performed at a temperature of not less than about 300xc2x0 C. and not greater than about 500xc2x0 C. The irradiation energy used in the irradiation of protons may be not greater than about 1 MeV.
According to the second arrangement, a semiconductor device, which uses a first-conductivity-type low impurity concentration substrate forming a first-conductivity-type low impurity concentration drift layer, and which comprises an element active region and a first electrode thereof formed at a first principal side of the substrate, and a high impurity concentration layer and a second electrode thereof formed at an outermost portion of a second principal side of the substrate, is characterized in that the first-conductivity-type high impurity concentration layer is an oxygen donor dope layer. If the high impurity concentration layer is the oxygen donor dope layer, the annealing process can be performed at a lower temperature than the fusing point of the first electrode, which is made of aluminum or the like. This enables the formation of the high impurity concentration layer at the second principal side, even after the adhesion of the first electrode layer, without any significant trouble.
A method for manufacturing this semiconductor device comprises the steps of: forming the element active region and the first electrode at the first principal side of the substrate; treating the second principal side of the substrate to reduce it to a predetermined thickness; implanting oxygen ions into the second principal side; and performing an annealing process to thereby form an oxygen donor dope layer. This semiconductor device can be manufactured at low cost, since it is possible to use an inexpensive n-type low impurity concentration FZ wafer. Due to the use of the oxygen ion implantation method, the range can be long and the maximum concentration point can be set in a deep portion. Thus, the impurity concentration inclines sharply in the oxygen donor dope layer as the high impurity concentration layer and at the boundary between the oxygen donor dope layer and the n-type low impurity concentration drift layer. This achieves a high characteristic of the same level as a semiconductor device that is manufactured by using an epitaxial wafer. The annealing process is preferably performed at a temperature of not less than about 300xc2x0 C. and not greater than about 500xc2x0 C.
According to the third arrangement, a method for manufacturing a semiconductor device, which uses a first-conductivity-type low impurity concentration substrate forming a first-conductivity-type low impurity concentration drift layer, and which comprises an element active region and a first electrode thereof formed at a first principal side of the substrate, and a high impurity concentration layer formed at an outermost portion of a second principal side of the substrate and a second electrode thereof, comprises the steps of: forming the element active region and the first electrode on the first principal side of the substrate; treating the second principal side of the substrate to reduce it to a predetermined thickness; implanting impurity ions from the second principal side; and irradiating the second principal side with light or laser while cooling the first principal side, thereby forming the high impurity concentration layer.
As the annealing process for forming the high impurity concentration layer at the second principal side, a lamp annealing or a laser annealing is performed with respect to the second principal side, while the first principal side having the first electrode is cooled (by jetting coolant gas, by using a heat sink, or the like). Therefore, an annealing temperature at the second principal side can be set at a higher temperature than the fusing point of aluminum (700xc2x0 C. or more), while a temperature gradient is ensured along the thickness of the substrate. Moreover, even the implanted impurities with a short range can be activated sufficiently and, thus, phosphorus or arsenic can be used as donor impurities. This semiconductor device can be manufactured at low cost, since it is possible to use an inexpensive n-type low impurity concentration FZ wafer. Due to the use of the proton ion implantation method, the range can be long and the maximum concentration point can be set in a deep portion. Thus, the impurity concentration inclines sharply in the high impurity concentration layer and at the boundary between the high impurity concentration layer and the drift layer. This achieves a high characteristic of the same level as a semiconductor device that is manufactured by using an epitaxial wafer.
The implantation energy in the implantation of phosphorus or arsenic ions may be not greater than about 1 MeV. The dose amount of the phosphorus or arsenic is preferably not less than about 1xc3x971013 cmxe2x88x922 and not greater than about 1xc3x971016 cmxe2x88x922.
The present invention may be applied, not only to diodes and MOSFETs, but also to general longitudinal semiconductor devices having an nxe2x88x92 drift layer and an n-type high impurity concentration layer (e.g., an ohmic contact layer) at the outermost portion of the second principal side. A third arrangement of the present invention is not restricted to the implantation of donor impurities. It is also possible to implant acceptor impurities (e.g., boron). Thus, the third arrangement of the present invention may be applied to general semiconductor devices having an nxe2x88x92 drift layer and an n-type high impurity concentration layer (e.g., an ohmic contact layer) at the outermost portion of the second principal side. The third arrangement may be applied to an ohmic contact layer (a high impurity concentration layer of any conductivity type) at the outermost portion of the reverse side, as is the case with a collector layer of a non-punch through IGBT (a conductivity modulation-type MOSFET).
The above object can also be accomplished by forming a high impurity concentration buffer layer at the reverse side (the second principal side) and a reverse-conductivity-type high impurity concentration layer at the outermost portion of the reverse side by a low-temperature process.
According to a fourth arrangement of the present invention, a method for manufacturing a semiconductor device, which uses a first-conductivity-type low impurity concentration substrate to form a first-conductivity-type low impurity concentration drift layer, and which comprises an element active region and a first electrode thereof formed at a first principal side of the substrate, a second-conductivity-type high impurity concentration layer and a second electrode thereof formed at an outermost portion of a second principal side of the substrate, and a first-conductivity-type impurity concentration buffer layer formed between the drift layer and the second-conductivity-type high impurity concentration layer, comprises the steps of: forming the element active region and the first electrode at the first principal side of the substrate; treating the second principal side of the substrate to reduce it to a predetermined thickness; irradiating protons from the second principal side; performing an annealing process to thereby form the buffer layer; implanting acceptor impurity ions from the second principal side; and performing an annealing process to thereby form the second-conductivity-type high impurity concentration layer.
The irradiation of protons and the low-temperature annealing process form an n-type defect layer as a lattice defect layer. The n-type defect layer functions substantially as an n-type high impurity concentration buffer layer. Since the range of the protons is long, the n-type defect layer is formed in a deeper portion than the second principal side. The annealing temperature for activating the n-type defect layer may be lower than the fusing point of the first electrode, made from a material such as aluminum, and thus, the n-type defect layer as the n-type high impurity concentration buffer layer can be formed even after the adhesion of the first electrode without any significant trouble.
In the annealing process for forming the second-conductivity-type high impurity concentration at the second principal side, energy (light or laser) is irradiated toward the second principal side for a short period of time while the first principal side having the first electrode is cooled (e.g., by jetting coolant gas or by using a heat sink). This ensures a temperature gradient across the thickness of the substrate, and the temperature at the first principal side can be set at a lower temperature (e.g., not greater than about 450xc2x0 C.) than the fusing point of the aluminum or like electrode metal, and the annealing temperature at the second principal side can be set at a higher temperature (e.g., about 700xc2x0 C. or more) than the fusing point of the electrode metal, usually aluminum or the like. This prevents the fusion of the first electrode and the increase in contact resistance between the first electrode and the silicon, and enables the sufficient activation of implanted impurities within a short range. Accordingly, this enables the use of an inexpensive low impurity concentration FZ wafer, and therefore achieves a significant reduction in the cost of the semiconductor device of the invention.
Additionally, it is possible produce a semiconductor device provided with an n-type high impurity concentration buffer layer, and this increases the current capacity and reduces the turnoff loss. It is, therefore, also possible to provide a less expensive semiconductor device that still exhibits high performance.
Either the buffer layer or the second-conductivity-type high impurity concentration layer may be formed first. The annealing process in the formation of the second-conductivity-type high impurity concentration layer is also used for the formation of the buffer layer. This would reduce the number of annealing steps. The irradiation energy used in the irradiation of protons may be not greater than about 1 MeV. The annealing process in the formation of the buffer layer may be performed at a temperature of about 300xc2x0 C. or more, but not greater than about 500xc2x0 C.
According to a fifth arrangement of the present invention, a method for manufacturing a semiconductor device which uses a first-conductivity-type low impurity concentration substrate forming a first-conductivity-type low impurity concentration drift layer, and which comprises an element active region and a first electrode thereof formed at a first principal side of the substrate, a second-conductivity-type high impurity concentration layer and a second electrode thereof formed at an outermost portion of a second principal side of the substrate, and a first-conductivity-type high impurity concentration buffer layer formed between the drift layer and the second-conductivity-type high impurity concentration layer, comprises the steps of: forming the element active region and the first electrode at the first principal side of the substrate and treating the second principal side of the substrate to reduce it to a predetermined thickness; implanting oxygen ions from the second principal side and performing an annealing process to thereby form the buffer layer; and irradiating acceptor impurity ions from the second principal side and performing an annealing process to thereby form the second-conductivity-type high impurity concentration layer.
According to a fifth arrangement of the present invention, the second-conductivity-type high impurity concentration layer is formed in the same manner as in the fourth arrangement, but the buffer layer is formed by implanting oxygen ions from the second principal side and performing a low-temperature annealing process. Due to the use of an oxygen ion implantation method, the range can be long and the maximum concentration point can be set in a deep portion to thereby form an oxygen donor dope layer as a buffer layer. In this case, an annealing temperature for forming the second-conductivity-type high impurity concentration layer can be set at a higher temperature (e.g., about 700xc2x0 C. or more) than the fusing point of aluminum.
Either the buffer layer or the second-conductivity-type high impurity concentration layer may be formed first. The annealing process in the formation of the second-conductivity-type high impurity concentration layer is also used for the formation of the buffer layer. This would reduce the number of annealing steps. The irradiation energy in the irradiation of protons may be not greater than about 1 MeV. The annealing process in the formation of the buffer layer may be performed at a temperature of not less than about 300xc2x0 C. and not greater than about 500xc2x0 C.
According to a sixth arrangement, a method for manufacturing a semiconductor device which uses a first-conductivity-type low impurity concentration substrate forming a first-conductivity-type low impurity concentration drift layer, and which comprises an element active region and a first electrode thereof formed at a first principal side of the substrate, a second-conductivity-type high impurity concentration layer and a second electrode thereof formed at an outermost portion of a second principal side of the substrate, and a first-conductivity-type high impurity concentration buffer layer formed between the drift layer and the second-conductivity-type high impurity concentration layer, the method comprising the steps of: forming the element active region and the first electrode at the first principal side of the substrate and treating the second principal side of the substrate to reduce it to a predetermined thickness; implanting donor impurity ions into the second principal side and performing an annealing process of irradiating energy to the second principal side while cooling the first principal side to thereby form the buffer layer; and implanting acceptor impurity ions into the second principal side and performing an annealing process to thereby form the second-conductivity-type high impurity concentration layer.
According to the sixth arrangement of the present invention, the second-conductivity-type high impurity concentration layer is formed in the same manner as in the fourth arrangement, but the buffer layer is formed by implanting donor impurity ions into the second principal side and performing an annealing process of irradiating energy (e.g., light or laser) toward the second principal side while cooling the first principal side. In the annealing process, an annealing temperature at the second principal side can be set at a higher temperature than the fusing point of aluminum (e.g., about 700xc2x0 C.), while a temperature gradient is ensured across the thickness of the substrate. This enables the sufficient activation of the implanted impurities with a short range. According to the sixth arrangement, in the annealing process for forming the second-conductivity-type high impurity concentration at the second principal side, energy (light or laser) is irradiated toward the second principal side for a short period of time, while the first principal side having the first electrode is cooled (e.g., by jetting coolant gas and by using a heat sink). This ensures a temperature gradient across the thickness of the substrate. As a result, the temperature at the first principal side can be set at a lower temperature than the fusing point of the aluminum or the like, and the annealing temperature at the second principal side can be set at a higher temperature than the fusing point of the aluminum or the like. This prevents the fusion of the first electrode or the like, and enables the sufficient activation of the implanted impurities with a short range. The energy may be irradiated for a short period of time.
Either the buffer layer or the second-conductivity-type high impurity concentration layer may be formed first. The annealing process in the formation of the second-conductivity-type high impurity concentration layer is also used for the formation of the buffer layer. This would reduce the number of annealing steps.
The donor impurity ions may be phosphorus or arsenic ions. The implantation energy used in the implantation of phosphorus or arsenic ions may be not greater than about 1 MeV. A dose amount of the phosphorus or arsenic may be not less than about 1xc3x971012 cmxe2x88x922 and not greater than about 1xc3x971015 cmxe2x88x922. Boron ions may be used as the acceptor impurity ions.
The present invention may be applied not only to an IGBT but also to a thyrister and a general longitudinal semiconductor device provided with the nxe2x88x92 drift layer and the p type high impurity concentration layer at the outermost portion of the second principal side. The sixth arrangement of the present invention may be applied to a general semiconductor device provided with the pxe2x88x92 drift layer and the n-type high impurity concentration layer at the outermost portion of the second principal side. Moreover, the present invention may be applied not only to the longitudinal semiconductor device provided with the drift layer and the buffer layer, but also to a general longitudinal semiconductor device provided with a first-conductivity-type low impurity concentration layer and a first-conductivity-type high impurity concentration layer.
According to a seventh arrangement of the present invention, a method for manufacturing a semiconductor device which uses a first-conductivity-type low impurity concentration substrate forming a first-conductivity-type low impurity concentration drift layer, and which comprises an element active region and a first electrode thereof formed at a first principal side of the substrate, and a high impurity concentration layer and a second electrode thereof formed at an outermost portion of a second principal side of the substrate, the method comprising the steps of: forming the element active region and the first electrode at the first principal side of the substrate; treating the second principal side of the substrate to reduce it to a predetermined thickness; and implanting first or second-conductivity-type impurity ions into the second principal side and performing an annealing process of irradiating energy to the second principal side while cooling the first principal side, thereby forming the high impurity concentration layer. The high impurity concentration layer may be formed not only in the outermost layer of the second principal side but also at a more internal area than the outermost layer of the second principal side. The first principal side is cooled, for example, by jetting coolant gas or by using a heat sink. To prevent the fusion of the first electrode, a temperature gradient is ensured across the thickness of the substrate. The energy may be irradiated for a short period of time.
According to this method, the temperature at the first principal side can be set at a lower temperature than the fusing point of aluminum or the like, and the annealing temperature at the second principal side can be set at a higher temperature than the fusing point of aluminum or the like, while the temperature gradient is ensured along the thickness of the substrate. This prevents the fusion of the first electrode or the like, and enables the sufficient activation of the implanted impurities with a short range. It is thus possible to use the inexpensive low impurity concentration FZ wafer and, therefore, to achieve a significant reduction in the cost of the semiconductor device of the invention.